`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   12:33:08 11/28/2012
// Design Name:   SCALE_UNIT
// Module Name:   D:/Workspace/xilinx workspace/HFM_DETECTOR/scale_simu.v
// Project Name:  HFM_DETECTOR
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: SCALE_UNIT
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module scale_simu;

	// Inputs
	reg clk;
	reg rst;
	reg [15:0] data_in;

	// Outputs
	wire [7:0] data_out;

	// Instantiate the Unit Under Test (UUT)
	SCALE_UNIT #(16,8,16) uut (
		.clk(clk), 
		.rst(rst), 
		.data_in(data_in), 
		.data_out(data_out)
	);
	
	integer i;
	always #10 clk = ~clk;

	initial begin
		// Initialize Inputs
		clk = 0;
		rst = 0;
		data_in = 0;

		// Wait 100 ns for global reset to finish
		#100
		
		rst = 1;
        
		// Add stimulus here
		for(i=0;i<50;i=i+1)
			#20 data_in = i*100;
			
	end
      
endmodule

